1. Field of the Invention
The invention relates to a method for allocating memory arrangement addresses to a buffer chip for one or more memory arrangements connected to the control chip. The invention also relates to a buffer chip which can be used to allocate memory arrangement addresses to memory arrangements.
2. Description of the Related Art
For very fast and high-density memory architectures, such as DDR-III (double data rate), “buffer chips” will be required in future. These buffer chips allow the “STUB bus”, as used today in DDR and DDR-II systems, to be replaced and instead point-to-point connections (P2P) or point-to-two-point connections (P22P) to be used. Such connections have the advantage that data transfer rates far beyond 1 Gbps are possible. By cascading the buffer chips, it also becomes possible to concatenate a large number of buffer chips with one another (daisy chain) and to produce memory systems having a very large number of memory arrangements on just one memory bus.
Normally, a buffer chip forms a memory module together with one or more memory arrangements, which are used in a computer system, for example. The memory modules can be in the form of DIMM modules, for example. Since the memory modules initially have no permanent address allocation, it is first of all necessary to allocate memory arrangement addresses to the respective memory modules when the computer system is started or after a reset. Since such memory modules with buffer chips are not connected to one another by means of a common bus, however, it is not possible to allocate the memory arrangement addresses using conventional methods. Instead, the memory modules are arranged in series, with each of the memory modules having an input and an output, and the output of one buffer chip being connected to the input of a subsequent buffer chip.